期末上機考(2)nand gate

module top;
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #400 clock1(a);
system_clock #50 clock1(d);
number  n1(e,a,b,c,d);
endmodule

module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5;
nand(a1,a,a);
nand(b1,b,b);
nand(c1,c,c);
nand(d1,d,d);
nand(x,b,c1,d1);
nand(w1,x,x);
nand(x2,b,c,d);
nand(w2,x2,x2);
nand(x3,a,c);
nand(w3,x3,x3);
nand(x4,b1,c,d1);
nand(w4,x4,x4);
nand(s1,w1,w1);
nand(s2,w2,w2);
nand(s3,w3,w3);
nand(s4,w4,w4);
nand(e,s1,s2,s3,s4);

endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

期末上機考(1)

module top;
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #400 clock1(a);
system_clock #50 clock1(d);
number  n1(e,a,b,c,d);
endmodule

module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(w1,b,c1,d1);
and(w2,b,c,d);
and(w3,a,c);
and(w4,b1,c,d1);
or(e,w1,w2,w3,w4);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

一位元家法器行為模式設計

module test_adder1;

 reg a,b;

 reg carry_in ;

 wire sum;

 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial

  begin

    carry_in = 0; a = 0; b = 0;

    # 100 if ( carry_out !== 0 | sum !== 0)

                $display(" 0+0+0=00 sum is WRONG!");

              else

                $display(" 0+0+0=00 sum is RIGHT!");

    carry_in = 0; a = 0; b = 1;

    # 100 if ( carry_out !== 0 | sum !== 1)

               $display(" 0+0+1=01 sum is WRONG!");

              else

               $display(" 0+0+1=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 0;

    # 100 if ( carry_out !== 0 | sum !== 1)

               $display(" 0+1+0=01 sum is WRONG!");

              else

               $display(" 0+1+0=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 1;

    # 100 if ( carry_out !== 1 | sum !== 0)

                $display(" 0+1+1=10 sum is WRONG!");

              else

                $display(" 0+1+1=10 sum is RIGHT!");

    carry_in = 1; a = 0; b = 0;

    # 100 if ( carry_out !== 0 | sum !== 1)

                $display(" 1+0+0=01 sum is WRONG!");

              else

                $display(" 1+0+0=01 sum is RIGHT!");

    carry_in = 1; a = 0; b = 1;

    # 100 if ( carry_out !== 1 | sum !== 0)

                $display(" 1+0+1=10 sum is WRONG!");

              else

                $display(" 1+0+1=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 0;

    # 100 if ( carry_out !== 1 | sum !== 0)

                $display(" 1+1+0=10 sum is WRONG!");

              else

                $display(" 1+1+0=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 1;

    # 100 if ( carry_out !== 1 | sum !== 1)

                $display(" 1+1+1=11 sum is WRONG!");

              else

                $display(" 1+1+1=11 sum is RIGHT!");

    $finish;

  end

endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);

 input a, b, carry_in;

 output carry_out, sum;

  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);

  assign carry_out = a&carry_in|a&b|b&carry_in;

endmodule

三位元多工器 結構模式

module top;

wire [2:0]  A, B, OUT;

wire SEL;

system_clock #6400 clock1(A[2]);

system_clock #3200 clock2(A[1]);

system_clock #1600 clock3(A[0]);

system_clock #800  clock4(B[2]);

system_clock #400  clock5(B[1]);

system_clock #200  clock6(B[0]);

system_clock #100  clock7(SEL);

mux3 M1(OUT,A,B,SEL);

endmodule

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL);

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module mux3(OUT, A, B, SEL);

output [2:0] OUT;

input [2:0] A,B;

input SEL;

mux hi (OUT[2], A[2], B[2], SEL);

mux mid(OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>7000)$stop;

endmodule

行為模式 2位元多工器