期末上機考(2)nand gate

module top;
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #400 clock1(a);
system_clock #50 clock1(d);
number  n1(e,a,b,c,d);
endmodule

module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5;
nand(a1,a,a);
nand(b1,b,b);
nand(c1,c,c);
nand(d1,d,d);
nand(x,b,c1,d1);
nand(w1,x,x);
nand(x2,b,c,d);
nand(w2,x2,x2);
nand(x3,a,c);
nand(w3,x3,x3);
nand(x4,b1,c,d1);
nand(w4,x4,x4);
nand(s1,w1,w1);
nand(s2,w2,w2);
nand(s3,w3,w3);
nand(s4,w4,w4);
nand(e,s1,s2,s3,s4);

endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule